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- The Q1 CC presentation and transcript can be found on the Atomera website
Q1 Summary: The company signed its first JDA and completed the Phase 4 tech transfer in Q1. The JDA customer is progressing towards releasing the technology to its business units which may lead to Phase 5 qualification on multiple nodes. All other Phase 3 customers continue to move forward and have experienced no delays even with industry wide capacity issues since these projects are considered a priority. There are 10 customers in Phase 3 and half have multiple Phase 3 engagements.
Recent groundbreaking MST work has demonstrated applicability for solving current issues in the 3nm fabs. More data and white paper to follow. The company also is receiving many industry inquiries on how MST can be used in older fabs to boost capacity 25%. It may be the only solution to solving the chip shortages going forward as older fabs are already running at over capacity and no one is building older fabs and current parts will not be migrated to newer fabs. MST is applicable to the complete Total Addressable Market(TAM) which is predicted to hit $750b by 2027.
- Atomera upcoming conference presentations
- Oppenheimer Emerging Growth :: May 11-12 2021
- Needham Tech & Media :: May 17-20 2021
- Stifel Cross Sector Insight :: June 8-10 2021
- CC Highlights
- $36.7m in cash. 2+ years of runway. $14m/year burn rate.
- JDA #1 signed and Phase 4 entered and Tech Transfer completed – $400k license fee paid.
- JDA #1 when Phase 4 completes will release to business units for Phase 5(multiple nodes)
- Current licenses (STMicro, AKM, large fabless) continue moving forward and pushing towards production. No delays.
- Other Phase 3 customers(7 customers) continue moving forward and pushing towards production. No delays.
- Recent MST work has proven applicability to 3nm fabs. Recent blog and future data coming soon!
- MST is getting many inquires in how it can help industry shortages by shrinking die size. One example showed a 25% die shrink that increased capacity 34%.
- MST Cad being widely adopted within industry and will greatly reduce time for future development programs
- EPI tool is installed at Arizona State University and is in final certification. Currently processing wafers.
Status of current Phase 3 and Phase 4 programs. There have been no delays and all are moving forward. While the JDA customers cover multiple nodes and take longer to move to Phase 5 since they are testing out the technology for all their business units to adopt. There are 10 customers in Phase 3 that can move to Phase 4 at any time. Those with multiple engagements will probably be JDAs covering multiple nodes. The following are quotes from the CC.
That being said, all of our existing customers continue moving forward on their development work with us. During discussions of incremental our new customer projects, we have started to hear rumblings of restrictions on R&D wafers because of tight capacity. At the same time, we are seeing increased requests to understand how MST can grow production volume through die size optimization. The current industry problems are a mixed blessing for us.
Our licensees continue to move forward toward commercialization with MST and we have several other phase three customers who we hope will move in that direction soon.
Beyond the JDA, all customer engagements continue moving forward. A focus on existing customers, ongoing travel restrictions and R&D wafer limitations will keep new customer growth from expanding significantly in the near term. However, we have been experiencing solid interest from both new and existing customers to learn how MST can be used in to expand their production volume and help solve both current and future capacity issues. It has been well reported in the news that many of the world’s manufacturers have experienced production stoppages for the lack of the semiconductor chips necessary to build their products.
Scott Bibaud — President and Chief Executive Officer
Yeah. The most important thing for us with existing customers is to get programs that we’re working on now push to completion and get into production. Although it’s great to start new programs with existing customers because generally you can get started faster, there’s lower barriers, you don’t have to go through all the formal contracts and so forth. But given a choice we’ll try to push our existing programs to production as best as we can rather than starting new ones
Chip shortage will last years. The TAM will almost double in the next 5 years. The MST solution allows older fabs to boost capacity with minimal investment. MST may be the only viable solution other than spending hundreds of billions on older fabs. In the slide example a 25% die shrink increased capacity 34%. The following are quotes from the CC.
One way they could get significant relief would be to use MST. Let’s look at a few different ways MST can be used solve industry problems. According to IC Insights, in 2020, more than 40% of monthly wafer capacity was to process nodes at 40 nanometers or above where more than half of that 180 nanometer or above, a manufacturing technology first introduced in the 1990s. Another 11% is in 20 to 40 nanometers, which the industry also categorized as legacy nodes.
These are the areas where the most help was needed, and MST is one of the only technologies with an ability to provide significant improvements in performance and die size for products in those process nodes. On this slide we show how at 180 nanometers MST SP is able to outperform an industry-standard designed by more than 30%. If we take those same mechanisms and direct them to die size reduction, MST is able to shrink a similar die by approximately 15 to 20%. Our ongoing development work continues to find ways to use MST to improve these numbers and thus, the expected savings.
The step function and costs to build a new facility is too large to consider but by encouraging their engineers to make new designs using MST, they will get 15 to 20% more chips out of the same number of wafers produced without it. Our economic analysis shows this will have the effect of increasing both revenue and profits for the fabs and their customers, while also providing a healthy royalty to Atomera. Remarkably MST should work even better at nodes smaller than the ones we talked about before.
We then traded off the performance improvement for die size reduction using MST on a typical NAND2 gate like the one shown here, it resulted in a 22 to 25% area reduction. Analog scaling with MST provided a 21% reduction. So, overall, you can see how these results can really move the needle on capacity improvement. We have been in discussions with many potential customers about using MST to help solve their production problems.
First mentioned in a Robert Mears(CTO) blog in April recent development work and test results demonstrated that MST is highly effective in the next generation fabs. Check out the recent blog. The following are quotes from the CC.
- Happy Earth Day!
- By Robert Mears, Atomera Founder and CTO
Although the opportunity in legacy nodes is quite exciting for Atomera, MST technology is also very well positioned to solve problems for customers at the leading edge.
As manufacturers attempt to make transistors with the smallest geometries, it’s important that junctions are sharp and well-defined. As Robert Mears’ blog post pointed out last week, MST does a much better job of that than other methods the industry is currently trying. We have previously been worried that MST, while very thin, may still be too big for these applications, so we tried making it much thinner and it still worked beautifully. Over the next few weeks, we will have more information about this development on our website and you can be sure that our customers are going to be hearing about it as well.
The EPI tool is housed at the Arizona State former Motorla fab which is also shared with Applied Materials. The fab is processing wafers and is finishing certification. Besides sharing the facility with Applied Materials this area is also the location for industry giants like TSMC, Intel and Samsung to just name a few. The following are quotes from the CC.
OK. So, our Epi tool is located at the Arizona State MacroTechnology Works center in Tempe, Arizona. It’s a world-class semiconductor facility used to be owned by Motorola, who I believe transferred it to Arizona state years ago. Beautiful state-of-the-art facility.
Now, why in Tempe, which is just outside of Phoenix? Phoenix is a little bit of a epitaxial center of excellence in the world. That’s where there are a lot of engineering — a lot of engineering town out there that does that. It’s also a site of a number of fabs. And when you run Epi you need to have the infrastructure that you need for a semiconductor fab including very large hydrogen tanks and other chemical suppliers that are nearby.
Our tool is set up. We are actually processing wafers in there and we’re qualifying our film. All that being said, we haven’t signed off a 100% on the full facility requirements yet. I know it’s been a long time, it seems like we’re always right around the corner.
Any due diligence from this site is for entertainment only and not a solicitation to buy or sell Atomera stock. Any estimates are just examples of what is possible and should not be considered financial advise. I have not been compensated in any way and will never be compensated for my reports.