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Any good investor will tell you the more you can learn about your investment the easier it is to make good investment decisions. With microcap stocks, that have yet to draw a huge number of analysts, digging deeply into a companies prospects can be both challenging and rewarding. With Atomera, a stock I was asked to look into over 5 years ago, there are a ton of clues that could be connected in many different ways but final validation will come when the first industry partner is announced as they head to production. Even the clues that can be found in the recent 10Qs showing the $400k tech transfer payment came from Asia Pacific and additional data indicating the payment very likely came from South Korea are still only speculation that the first JDA is with SK Hynix or Samsung. A recent blog from Applied Materials could be another important clue. If it turns out they are validating Atomera’s MST technology it is another step closer to industry wide adoption. Imagine one of the worlds largest semiconductor equipment providers validating Atomera’s MST technology. They have been partnered together for years so its just a matter of time before details of their partnership become public.
- Applied Materials Blog
- Not All Semiconductor Innovation Occurs at the Leading Edge
- Mike Chudzik, Ph.d, August 27,2021
- Atomera Blog 10/2020
- Architecture Faster, Cooler Less-Expensive IoT SoCs
Because the added oxygen layers reduce leakage, the amount of halo doping needed is also reduced, lowering the 1/f noise. The analog circuitry needed for radios and sensor-signal conditioning are particularly susceptible to noise, so any reduction improves performance.
The one area of the Applied Materials blog that stands out is the discussion on CMOS Imagers. In an upcoming seminar Applied Materials will discuss the challenges of next generation image sensors and how to overcome these challenges. On the Atomera website they specifically explain the benefits of using MST in image sensors and also list their high number of patents they own in this space.
CMOS Image Sensors Need Materials Engineering to Continue Scaling
CMOS image sensor (CIS) arrays enable the multiple cameras in today’s smartphones and smart cars. Manufactured at nodes between 45nm and 90nm, they’re arranged into millions of individual light sensitive pixels in groups of three—one each for blue, green and red.
The conventional means for achieving higher CMOS image sensor resolution is to use a planar scaling process that reduces feature sizes and allows more pixels to be squeezed into a given area. A major obstacle to this manufacturing approach is maintaining sufficiently high levels of dynamic range. This refers to the ability to capture very low light and bright light at the same time, which becomes more difficult because smaller pixels are prone to saturation that can introduce image artifacts.
To enable continued 2D pixel scaling through the next several process nodes, smartphone camera designers will require innovations in materials engineering that enable new isolation and passivation techniques. For example, as more pixels share the same die area they are increasingly subject to crosstalk that can lead to pixel noise and poor image quality. Deep isolation trenches between pixels are required to separate individual signals; however, as planar pixel scaling progresses, these isolation trenches become taller and thinner, creating extremely high aspect ratios. Today these ratios are in the range of 40:1 but could soon reach 60:1 and even 100:1.
From the above Applied Materials blog its obvious the issues being addressed by Applied Materials are the same benefits from adopting MST technology. As the image sensors go to higher resolution the issues that MST can solve only become of increasing importance.
Also of importance is the high number of patents that have been issued to Atomera over the last few years in the area of CMOS Imagers. The one highlighted below seems to directly correlate with the Applied Materials blog.
- CMOS Image Sensor With Buried Superlattice Layer To Reduce Crosstalk
- Patent number: 10304881 June 20th, 2019
- CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
- Patent number: 10615209 April 7, 2020
- Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
- Patent number: 10608027 March 31st, 2020
- Method for making CMOS image sensor including pixels with read circuitry having a superlattice
- Patent number: 10529768 January 7, 2020
- CMOS image sensor including pixels with read circuitry having a superlattice
- Patent number: 10529757 January 7,2020
Any due diligence from this site is for entertainment only and not a solicitation to buy or sell Atomera stock. Any estimates are just examples of what is possible and should not be considered financial advise. I have not been compensated in any way and will never be compensated for my reports.